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Brief history and overview
Programming model and register set The programming model and register set are conventional and similar to many other processors, such as the related x86 family. The 8080 compatible registers AF,BC,DE,HL are duplicated as two separate banks in the Z80, where the processor can quickly switch from one bank to the other; a feature useful for speeding up responses to single level, high priority interrupts. This makes sense as the Z80 (like, for instance, the 6502) was really intended for embedded use, not for personal computers, or the yet-to-be invented home computers. The 8080 compatible registers: There is no direct access to the alternate registers, instead two special instructions, EX AF,AF' and EXX, each toggles one of two multiplexer flipflops; this enables fast context switches for interrupt service routines: EX AF,AF' may be used alone (for really simple and fast interrupt routines) or together with EXX to swap the whole AF,BC,DE,HL set; still much faster than pushing the same registers on the stack (slower, or lower priority, interrupts normally use the stack to store registers). The refresh register, R, increments each time the CPU fetches an opcode (or opcode prefix) and has therefore no simple relationship with program execution. This has sometimes been used to generate pseudorandom numbers in games, and also in software protection schemes. It has also been employed as a "hardware" counter in some designs; a famous example of this is the ZX81, which lets it keep track of character positions on the TV screen by triggering an interrupt at wrap around (by connecting INT to A6). The interrupt vector register, I, is used for the Z80 specific mode 2 interrupts (selected by the im 2 instruction). It supplies the base address for a table of service routine addresses which are selected via a pointer sent to the CPU during an interrupt acknowledge cycle. The pointer identify a particular peripheral chip and/or peripheral function or event, where the chips are normally connected in a so called daisy-chain for priority resolution. Like the refresh register, this register has also sometimes been used creatively. Background The first Intel 8008 assembly language was based on a very simple (but systematic) syntax inherited from the Datapoint 2200 design. This original syntax was later transformed into a new, somewhat more traditional, assembly language form for this original i8008 chip. At about the same time, the assembly language was also extended to accommodate the new addressing possibilities in the more advanced 8080 chip . In this process, the mnemonic L, for load, was replaced by various abbreviations of the words load, store and move, intermixed with other symbolic letters; the mnemonic M, for memory (referenced by HL), was lifted out from within the instruction mnemonic and became an operand; registers also became very inconsistently denoted, sometimes by abbreviated operands (MVI D, LXI H etc), or within the instruction mnemonic itself (LDA, LHLD etc), or both (LDAX B, STAX D etc). Datapoint 2200 & i8008 i8080 Z80 i8086 (ca -1973) (ca 1974) (1976) (1978) LBC MOV B,C LD B,C MOV BL,CL -- LDAX B LD A,(BC) MOV AL,BX LAM MOV A,M LD A,(HL) MOV AL,BP LBM MOV B,M LD B,(HL) MOV BL,BP -- STAX D LD (DE),A MOV DX,AL LMA MOV M,A LD (HL),A MOV BP,AL LMC MOV M,C LD (HL),C MOV BP,CL LDI 56 MVI D,56 LD D,56 MOV DL,56 LMI 56 MVI M,56 LD (HL),56 MOV byte ptr BP,56 -- LDA 1234 LD A,(1234) MOV AL,1234 -- STA 1234 LD (1234),A MOV 1234,AL -- -- LD B,(IX+56) MOV BL,SI+56 -- -- LD (IX+56),C MOV SI+56,CL -- -- LD (IY+56),78 MOV byte ptr DI+56,78 -- LXI B,1234 LD BC,1234 MOV BX,1234 -- LXI H,1234 LD HL,1234 MOV BP,1234 -- SHLD 1234 LD (1234),HL MOV 1234,BP -- LHLD 1234 LD HL,(1234) MOV BP,1234 -- -- LD BC,(1234) MOV BX,1234 -- -- LD IX,(1234) MOV SI,1234 Illustration of four syntaxes, using samples of equivalent, or (for 8086) very similar, load and store instructions. The new syntax According to Masatoshi Shima, certain people within Zilog wanted a "computer oriented" image for the company, and also felt they needed to "differentiate" their first product from the 8080. Intel had also copyrighted their assembly mnemonics. Yet another assembly syntax was therefore developed, but this time with a more systematic approach: These principles made it straighforward to find names and forms for all new Z80 instructions, as well as orthogonalizations of old ones, such as LD BC,(1234) above. It is interesting to see the resemblance between Z80 and 8086 syntax, as illustrated by the table. Apart from naming differences, and despite a certain discrepancy in basic register structure, the two are virtually isomorphous for a large portion of Z80 instructions. Instruction set and encoding The Z80 uses 252 out of the available 256 codes as single byte opcodes; the four remaining codes are used extensively as opcode prefixes; CB and ED enables extra instructions and DD or FD selects IX+d or IY+d (in some cases without displacement d) in place of HL. This scheme gives the Z80 a large number of permutations of instructions and registers; ZiLOG categorizes these into 158 different "instruction types", 78 of which are the same as those of the Intel 8080 (allowed operation of 8080 programs on a Z80). The ZiLOG documentation further groups instructions into the following categories: The bit set, reset, and test instructions are well adapted to I/O control. No multiply instruction is available in the original Z80. Different sizes and variants of additions, shifts, and rotates have somewhat differing effects on flags because the flag-influencing properties of the 8080 had to be copied for compatibility. Load instructions does not affect the flags (except for the special purpose I and R register loads). Undocumented instructions The index registers, IX and IY, were intended as flexible 16 bit pointers, enhancing the ability to manipulate memory, stack frames and data structures. Officially, they were treated as 16 bit only. In reality, they were implemented as a sort of copy of the HL register which is accessible as 16 bits or as a pair of 8 bit pair registers (H and L). Even the binary opcodes (machine language) were identical, but preceded by a new opcode prefix, as mentioned above. ZiLOG published the opcodes and related mnemonics for the intended functions, but did not document the fact that every opcode that allowed manipulation of the H and L registers was equally valid for the 8 bit portions of the IX and IY registers. As an example, the opcode 26h followed by an immediate byte value (LD H,n) will load that value into the H register. Preceding this two-byte instruction with the IX register's opcode prefix DD, would instead result in the most significant 8 bits of the IX register being loaded with that same value. There are several other undocumented instructions as well. Instruction execution As in all microprocessors, each instruction is divided into several steps which are usually termed machine cycles (M-cycles). Z80 needs between one and six M-cycles to execute a particular instruction as each M-cycle corresonds roughtly to one memory access and/or internal operation. Many instructions actually end during the M1 of the next instruction which is known as a fetch/execute overlap. Examples of typical instructions (R=read, W=write) Total M-cycles instruction M1 M2 M3 M4 M5 M6 1 INC A opcode 2 ADD A,100 opcode 100 3 ADD HL,DE opcode internal internal 4 SET 5,(HL) prefix opcode R(HL), set W(HL) 5 LD (IX+102),103 prefix opcode 102 103,add W(IX+102) 6 INC (IY+104) prefix opcode 104 add R(IY+104),inc W(IY+104) The Z80 machine cycles are sequenced by an internal state machine which builds each M-cycle out of 3,4, or 5 discrete steps (i.e. clock cycles) depending on context. This avoids cumbersome asynchronous logic and makes the control signals behave consistently at a wide range of clock frequencies. Naturally, it also means that a higher frequency (approximately 2.5 times) crystal must be used than without this subdivision of machine cycles. It does not imply higher requirements on memory access times however, as the Z80 combines at least two full clockcycles to form a long memory access period (the M1-signal) which would typically last only a fraction of a clock cycle in more asynchronous design. Moreover, affordable memory chips (especially ROM & FLASH) are generally significantly slower than the state machine sub-cycles (clock cycles) used in microprocessors, and the shortest machine cycle time that could safely be used is limited by memory access times in most embedded (and home computer) designs. Compatible peripherals Zilog introduced a number of peripheral parts for the Z80, which all supported the Z80's interrupt handling system and I/O address space. These included the CTC (Counter-Timer-Circuit), the SIO (Serial Input Output), the DMA (Direct Memory Access), the PIO (Parallel Input-Output) and the DART (Dual Asynchronous Receiver Transmitter). As the product line developed, low-power, high-speed and CMOS versions of these chips were produced. In the same manner as the x86 family, but unlike contemporary 8-bit processors, like the Motorola 6800 and Mos Technology 6502, the Z80 and 8080 had a separate control line and address space for I/O instructions. While some Z80-based computers used "Motorola-style" memory mapped input/output devices, usually the I/O space was used to address one of the many Zilog peripheral chips compatible with the Z80. Zilog I/O chips supported the Z80's new mode 2 interrupts (see description above) which simplified interrupt handling for large numbers of peripherals. Undocumented 16 bit I/O-addressing The Z80 was officially described as supporting 16 bit (64k bytes) memory addressing, and 8 bit (256 ports) I/O-addressing. Looking carefully at the hardware reference manual, it can be seen that several I/O instructions, OUT (C),A for example, assert the contents of the entire 16 bit BC register to the address bus. An orthodox design would maybe decode the entire 16 bit address bus on I/O operations in order to take advantage of this feature, but it has also been used to minimize hardware requirements, see ZX81. Second sources
Derivatives Currently produced: No longer produced: Some index register instructions in the original Z80 are no faster than equivalent sequences of simpler operations, merely saving space, not time; the 10-year-newer Z180 design could afford more "chip area", permitting a somewhat more efficient implementation (using a wider ALU, among other things). However, it was not until 2001 and the advent of the fast pipelined eZ80 that those instructions finally became approximately as cycle-efficient as it is technically possible to make them, i.e. given the Z80 encodings combined with the capability to do an 8-bit read or write every clock cycle. FPGA and ASIC versions A commercial, functionally equivalent, CPU core is the Evatronics CZ80CPU, available as synthesizable VHDL or Verilog source code, for high volume ASICs, or as post-synthesis EDIF netlists, for low volume FPGAs from Actel, Altera, Lattice or Xilinx. Free versions are the T80 and TV80, available as VHDL and Verilog sources under a BSD style license. The VHDL version, once synthesized, can be clocked up to 35 MHz on a Xilinx Spartan II FPGA. For large production series, it's much cheaper to use a traditional solution (or ASIC) than an FPGA, however. Software emulation Software emulation of the Z80 instruction set on modern PCs runs faster than the original Z80 CPU ran and is used for home computer simulators (such as ZX Spectrum and Amstrad CPC) and also for video game emulators such as MAME, which executes 1980s vintage video games. In desktop computers During the late 1970s and early 1980s, the Z80 was used in a great number of fairly anonymous business-oriented machines with the CP/M operating system; a CPU/OS combination that dominated the market in much the same way that Windows based machines do today. Two well-known examples of Z80+CP/M business computers are the portable Osborne 1 and the Kaypro series. Research Machines manufactured the 380Z and 480Z microcomputers which were networked with a thin Ethernet type LAN and CP/NET in 1981. Other manufacturers of such systems included Televideo, Xerox and a number of more obscure firms. Some systems used multi-tasking operating system software to share the one processor between several concurrent users. Home computers using the Z80 include the following: In embedded systems and consumer electronics The Zilog Z80 has long been a popular microprocessor in embedded systems and microcontroller cores, where it remains in widespread use today. The following list provides examples of such applications of the Z80, including uses in consumer electronics products. Industrial/professional: Consumer electronics: See also | |||||||||||||
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