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Power-on self-test (POST) is the common term for a computer's, router's or printer's pre-boot sequence. The same basic sequence is present on all computer architectures. It is the first step of the more general process called initial program load (IPL), booting, or bootstrapping. The term POST has become popular in association with and as a result of the proliferation of the PC. It can be used as a noun when referring to the code that controls the pre-boot phase or when referring to the phase itself. It can also be used as a verb when referring to the code or the system as it progresses through the pre-boot phase. Alternatively this may be called "POSTing". General internal workings On the PC, the main duties of POST are handled by the BIOS, which may hand some of these duties to other programs designed to initialize very specific peripheral devices, notably for video and SCSI initialization. These other duty-specific programs are generally known collectively as option ROMs or individually as the video BIOS, SCSI BIOS, etc. The principal duties of the main BIOS during POST are as follows: The BIOS will begin its POST duties when the CPU is reset. The first memory location the CPU tries to execute is known as the reset vector. In the case of a hard reboot, the northbridge will direct this code fetch (request) to the BIOS located on the system flash memory. For a warm boot, the BIOS will be located in the proper place in RAM and the northbridge will direct the reset vector call to the RAM. During the POST flow of a contemporary BIOS, one of the first things a BIOS should do is determine the reason it is executing. For a cold boot, for example, it may need to execute all of its functionality. If, however, the system supports power savings or quick boot methods, the BIOS may be able to circumvent the standard POST device discovery, and simply program the devices from a preloaded system device table. The POST flow for the PC has developed from a very simple, straightforward process to one that is complex and convoluted. During POST, the BIOS must integrate a plethora of competing, evolving, and even mutually exclusive standards and initiatives for the matrix of hardware and OSes the PC is expected to support. However, the average user still knows the POST and BIOS only through its simple visible memory test and setup screen. Fundamental structure In the case of the IBM PC compatible machines, the main BIOS is divided into two basic sections. The POST section, or POST code, is responsible for the tasks mentioned above, and the environment POST constructs for the OS is known as the runtime code, the runtime BIOS, or the runtime footprint. Primarily these two divisions can be distinguished in that POST code should be flushed from memory before control is passed to the target OS while the runtime code remains resident in memory. This division may be a misleading oversimplification, however, as many Runtime functions are executed while the system is POSTing. Error reporting The original IBM BIOS reported errors detected during POST by outputting a number to a fixed I/O port address, 80. Using a logic analyzer or a dedicated POST card, an interface card that shows port 80 output on a small display, a technician could determine the origin of the problem. (Note that once an operating system is running on the computer, the code displayed by such a board is often meaningless, since some OSes, e.g. Linux, use port 80 for I/O timing operations.) In later years, BIOS vendors used a sequence of beeps from the motherboard-attached loudspeaker to signal error codes. Original IBM POST error codes POST AMI BIOS beep codes Reference: AMIBIOS8 Check Point and Beep Code List, version 1.71, last updated 7 June 2005 POST beep codes on CompTIA A+ Hardware Core exam These POST beep codes are covered specifically on the CompTIA A+ Core Hardware Exam: IBM POST diagnostic code descriptions See also | |||||||
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