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Instruction set Programmers liked the PDP-11 design because it had a highly-orthogonal instruction set which allowed a programmer to separately memorize all of the operations and the methods of accessing operands. They could then predict that any access method (or "addressing mode") would work with any operation; they did not have to learn a list of exceptions or special cases in which an operation had a special or restricted set of addressing modes. The instruction set architecture of the PDP-11 influenced the idiomatic use of the C programming language. The register increment and decrement addressing modes correspond to the --i and i++ constructs in C. If i and j were both register variables, an expression such as In some logical sense, the set of addressing modes provided one "basis", and the set of operations provided another. Each two-operand instruction was separated into two six-bit operand identifiers (each consisting of a three-bit register number, and a three-bit addressing mode) and a four-bit op-code; single-operand instructions had one six-bit operand identifier, and a ten-bit op-code. All op-codes operated with any operand identifier address mode (or combination of them, for the two-operand instructions). Of the 8 registers (numbered 0 through 7), 7 were general-purpose and could be used for most purposes, although register 6 was specially recognized by the hardware as the stack pointer for some instructions; register 7 was the program counter. This latter innovation, together with some of the addressing modes, provided constants, absolute addresses, and relative (position independent) addressing. 16-bit words were stored little-endian with least significant bytes first. 32-bit words were often stored in an unusual middle-endian format. Due to the popularity of the PDP-11, this format is still sometimes referred to as pdp-endian. No dedicated I/O bus In the most radical departure from other, earlier computers, the PDP-11 had no dedicated bus for input/output; it had only a memory bus called the Unibus. All input and output devices were mapped to addresses in memory, so no special I/O instructions were needed. The interrupt system was intentionally designed to be as simple as possible, while ensuring that no event in an interrupt sequence could be missed. A device would request an interrupt by asserting a common input into one of four priority lines; the processor would respond over an interrupt daisy chain grant line, one for each priority level. (A daisy chain is a sequence of logic gates arranged in series to order events. Generally the first logic gate has first access to the grant. The daisy chain order established the order of the devices at that priority level.) In the case of the PDP-11 design, this meant that the interrupt grant order was determined by how close the physical hardware was to the CPU on the bus. When the CPU responded, the device would place its vector address on the bus; this was the address of a 4-byte block of memory. The CPU would then load the status register and program counter from the vector table; the new contents of the status register would generally temporarily disable interrupts. The address in the program counter would be the starting address of the code to run for the interrupt. The interrupt code would then service the device, and in the process, write to the interrupting device to re-enable the interrupt signal. Finally, a special RTI (return from interrupt) instruction would return the CPU to where it was before the interrupt (which might have been in a lower-priority interrupt). Note that this process prevents loss of interrupts; at every stage, if the interrupt is not serviced, it remains in place, to be sensed on the next cycle. If a sequence were erroneously started, the CPU would time out, generating a special spurious interrupt; the spurious interrupt would warn users of bad hardware. Designed for mass production Finally, the PDP-11 was designed to be produced in a factory by semiskilled labor. All of the dimensions of its pieces were relatively non-critical. It used a wire-wrapped backplane. That is, the printed circuit board plugged into a backplane connector. The backplane connector had terminals that could be connected to by wrapping wires around them. The terminal would cut the insulation around the wire and bite into the wire to form a gas-tight (i.e. corrosion-proof, therefore reliable) connection. The connector blocks were very similar to telephone connection blocks. The LSI-11 The LSI-11 was the first PDP-11 model produced using large-scale integration; the entire CPU was contained on 4 LSI chips made by Western Digital (the MCP-1600 chip set). It used a bus which was a close variant of the Unibus called the Q-Bus; it differed from the Unibus primarily in that addresses and data were multiplexed onto a shared set of wires, as opposed to having separate sets of wires, as in the Unibus. It also differed slightly in how it addressed I/O devices and it eventually allowed a 22-bit physical address (whereas the Unibus only allowed an 18-bit physical address) and block-mode operations (which the Unibus did not support). The CPU's microcode includes a debugger that directly communicated to a standard RS-232 terminal. This was innovative because the microcode is the part of the irreducible guts of the computer, a critical part of the control unit. If it doesn't work, there is no computer. The debugger provided a way to examine the computer's registers, memory and input and output devices. Thus, if the CPU worked at all, it was possible to examine and correct the computer's internal state. The built-in debugger avoided the expense and inconvenience of a front panel with an array of switches and lights, which was then the typical way to enter digital data into a near-dead computer. The microcode also included a generic bootstrap, to which all DEC disk drives were compatible. These two innovations meant that most of the time, the computer just worked. If it did not boot from its big disk, it would boot from its floppy. If the hardware worked at all, it talked to you through a terminal in a familiar way. The decline of the PDP-11 The basic design was extremely good, and was continually updated to use newer technologies. Ultimately, however, the 16-bit architecture proved to be a limitation which could not be overcome by tweaks and add-ons. While some models could support larger physical address spaces using memory mapping hardware, all programs were restricted to a 16-bit virtual address space with only 64K bytes of memory. When inexpensive VLSI memory chips became available in the 1980s, PDP-11 software was not capable of using large amounts of memory easily. DEC's own successor to the PDP-11, the VAX-11 (for "Virtual Address Extension (to the PDP-11)") addressed all of these issues, but was initially aimed at the high-end time sharing market. The early VAXes contained a PDP-11 compatibility mode, so could be considered PDP-11s for application programmers. Intel's 8086 and 8088 supported a 4 bit "segment" extension to its 16-bit address, which permitted direct addressing of up to 1M of memory without the overhead of a total 32-bit redesign. This was good enough to serve the growing IBM PC compatible market, though it would soon outgrow even the 1M limit as well before the 80286, which supported larger segmented address spaces, and the 80386, which supported a 32-bit linear address space, became available. As engineers migrated to architectures that supported a larger address space, 32-bit computing began to be supported on microprocessor chips such as the Motorola 68000 and Intel 80386 processors and their successors; eventually the economics of large-scale production of those chips made them so cheap there was no cost advantage for the PDP-11. A line of personal computers based on the PDP-11, the DEC Professional series failed, along with 2 other DEC PC offerings. DEC discontinued the final PDP-11 models in 1997. The PDP-11 design and operating system licenses were finally sold to Mentec, Inc., an Irish producer of LSI-11 based boards for Q-Bus and ISA architecture personal computers. By the late 1990s, not only DEC, but most of the New England computer industry which was built around minicomputers like the PDP-11 also collapsed in the face of UNIX and Windows servers. Architectural details The following information is found in DEC's PDP-11 Processor Handbook (see Gordon Bell's 1969 edition). General register addressing modes (R is a general register, 0 to 7; (R) is the contents of that register.) 0. Register - the value is to or from a register: OPR RR contains operand 1. Register deferred - register is used as a memory address to read or write: OPR (R)R contains address 2. Autoincrement: OPR (R)+R contains address, then increment (R) 3. Autoincrement deferred: OPR @(R)+R contains address of address, then increment (R) by 2 4. Autodecrement: OPR -(R)Decrement (R), then R contains address 5. Autodecrement deferred: OPR @-(R)Decrement (R) by 2, then R contains address of address 6. Index: OPR X(R)(R)+X is address, second word of instruction 7. Index deferred: OPR @X(R)(R)+X is address (second word) of address Program counter addressing modes The program counter (PC) can also be used as a general purpose register, providing the following effectively additional addressing modes, using the mechanisms of the addressing modes above: 2. Immediate: OPR 3. Absolute: OPR @ 6. Relative: OPR APC+2+X is address. PC+2 is updated PC 7. Relative deferred: OPR @APC+2+X is address of address. PC+2 is updated PC PDP-11 instructions Assembly Language Programming Example
PDP-11 models The PDP-11 processors tended to fall into several natural groups depending on the original design upon which they are based and which I/O bus they used. Within each group, most models were offered in two versions, one intended for OEMs and one intended for end-users. Unibus models The following models used the Unibus as their principal bus: Q-bus models The following models used the Q-Bus as their principal bus: Models without standard bus The PDT series were desktop systems marketed as "smart terminals". The /110 and /130 were housed in a VT100 terminal enclosure. The DEC Professional series were desktop PCs intended to compete with IBM's earlier 8088 and 80286 based personal computers. The models were equipped with 5 1/4" floppy disk drives and hard disks, except the 325 which had no hard disk. The CPUs were from the LSI-11 line running P/OS, which was essentially RSX-11M+ with a menu system on top. As the design was intended to avoid software exchange with existing PDP-11 models, their ill fate in the market was no surprise for anyone except DEC. Models that were planned but never introduced Special purpose versions
Clandestine clones The PDP-11 was sufficiently popular that several unauthorized clones were produced behind the Iron curtain. At least some of these were pin-compatible with DEC's PDP-11s and could share peripherals and system software. These include: Operating systems Several operating systems were available for the PDP-11 From Digital: From third parties: PDP-11 Units Still in Service The computer system in the METROL metropolitan train control centre in Melbourne, Australia is still in regular commercial service. This system runs an operating system coded in Swedish PASCAL for the creation of train timetables, fleet management and passenger information displays. | |||||||||||||
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