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In computing, an interrupt is an asynchronous signal from hardware indicating the need for attention or a synchronous event in software indicating the need for a change in execution. A hardware interrupt causes the processor to save its state of execution via a context switch, and begin execution of an interrupt handler. Software interrupts are usually implemented as instructions in the instruction set, which cause a context switch to an interrupt handler similarly to a hardware interrupt. Interrupts are a commonly used technique for computer multitasking, especially in real-time computing. Such a system is said to be interrupt-driven. An act of interrupting is referred to as an interrupt request.
Overview Hardware interrupts were introducted as a way to avoid wasting the processor's valuable time in polling loops, waiting for external events. Instead, an interrupt signals the processor when an event occurs, allowing the processor to process other work while the event is pending. Software interrupts were introduced as a mechanism for access to shared system routines that may also execute at higher privilege levels. Interrupts may be classified into one of two categories: Interrupts may be implemented in hardware as a distinct system with control lines, or they may be integrated into the memory subsystem. If implemented in hardware, a Programmable Interrupt Controller (PIC) or Advanced Programmable Interrupt Controller (APIC) is connected to both the interrupting device and to the processor's interrupt pin. If implemented as part of the memory controller, interrupts are mapped into the system's memory address space. Interrupts can be categorized into the following types: software interrupt, maskable interrupt, non-maskable interrupt (NMI), interprocessor interrupt (IPI), and spurious interrupt. Processors typically have an internal interrupt mask which allows software to ignore all external hardware interrupts while it is set. This mask may offer faster access than accessing an IMR in a PIC, or disabling interrupts in the device itself. In some cases, such as the x86 architecture, disabling and enabling interrupts on the processor itself acts as a memory barrier, in which case it may actually be slower. The phenomenon where the overall system performance is severely hindered by excessive amounts of processing time spent handling interrupts is called an interrupt storm or live lock. Level-triggered A level-triggered interrupt is a class of interrupts that are triggered by a high level (1), or low level (0) of the interrupt request line. An assertion of the line changes it from low to high or high to low. This class of interrupts allows multiple devices to efficiently share the same interrupt line. Typically, the processor samples the interrupt input at predefined times during each bus cycle such as state T2 for the Z80 microprocessor. If the interrupt isn't active when the processor samples it, the CPU doesn't see it. One possible use for this type of interrupt is to minimize spurious signals from a noisy interrupt line. Edge-triggered An edge-triggered interrupt is a class of interrupts that are triggered on either a falling edge (1 to 0), or (usually) a rising edge (0 to 1) of the assertion of the interrupt request line. This type of interrupt is useful for a fleeting signal that doesn't last long enough for the processor to recognize it using polled I/O or for when one is interested in only when a signal first becomes active - whether it be a long or short-lasting signal. Multiple devices typically cannot share an edge-triggered interrupt line. Because the generation of another interrupt will go unnoticed, devices in such a configuration could go unserviced. The ISA bus in particular is known for this issue. Many ISA cards cannot be probed for interrupt status: many will stop responding or lockup the system if serviced when they did not generate an interrupt. Therefore, special care must be taken to insure such systems do not share interrupt lines. Hybrid The last interrupt type is a hybrid, where the hardware not only looks for an edge, but it also verifies that the interrupt signal stays active for a certain period of time. A common hybrid interrupt is the NMI (non-maskable interrupt) input. Because NMIs generally signal major-or even catastrophic-system events, a good implementation of this signal tries to ensure that the interrupt is valid by verifying that it remains active for a period of time. This 2-step approach helps to eliminate false interrupts from affecting the system. Typical uses Typical interrupt uses include the following: system timers, disks I/O, power-off signals, and traps. Other interrupts exist to transfer data bytes using UARTs or Ethernet; sense key-presses; control motors; or anything else the equipment must do. A classic system timer interrupt interrupts periodically from a counter or the power-line. The interrupt handler counts the interrupts to keep time. The timer interrupt may also be used by the OS's task scheduler to reschedule the priorities of running processes. Counters are popular, but some older computers used the power line frequency instead, because power companies in most Western countries control the power-line frequency with an atomic clock. A disk interrupt signals the completion of a data transfer from or to the disk peripheral. A process waiting to read or write a file starts up again. A power-off interrupt predicts or requests a loss of power. It allows the computer equipment to perform an orderly shutdown. Interrupts are also used in typeahead features for buffering events like keystrokes. See also | ||||||||
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