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An instruction set, or instruction set architecture (ISA), is the part of the computer architecture related to programming, including the native data types, instructions, registers, addressing modes, memory architecture, interrupt and exception handling, and external I/O. An ISA includes a specification of the set of opcodes (machine language), the native commands implemented by a particular CPU design. Instruction set architecture is distinguished from the microarchitecture, which is the set of processor design techniques used to implement the instruction set. Computers with different microarchitectures can share a common instruction set. For example, the Intel Pentium and the AMD Athlon implement nearly identical versions of the x86 instruction set, but have radically different internal designs. This concept can be extended to unique ISAs like TIMI (Technology-Independent Machine Interface) present in the IBM System/38 and IBM AS/400. TIMI is an ISA that is implemented as low-level software and functionally resembles what is now referred to as a virtual machine. It was designed to increase the longevity of the platform and applications written for it, allowing the entire platform to be moved to very different hardware without having to modify any software except that which comprises TIMI itself. This allowed IBM to move the AS/400 platform from an older CISC architecture to the newer POWER architecture without having to rewrite any parts of the OS or software associated with it. Instruction set design When designing microarchitectures, engineers use Register Transfer Language (RTL) to define the operation of each instruction of an ISA. Historically there have been 4 ways to store that description inside the CPU: An ISA can also be emulated in software by an interpreter. Due to the additional translation needed for the emulation, this is usually slower than directly running programs on the hardware implementing that ISA. Today, it is common practice for vendors of new ISAs or microarchitectures to make software emulators available to software developers before the hardware implementation is ready. Some instruction set designers choose the "0xff" all-ones instruction (and the "00" all-zeros instruction) to be some kind of software interrupt *. Fast virtual machines are much easier to implement if an instruction set meets the Popek and Goldberg virtualization requirements. On systems with multiple processors, non-blocking synchronization algorithms are much easier to implement if the instruction set includes support for something like "fetch-and-increment" or "load linked/store conditional (LL/SC)" or "atomic compare and swap". Code density In early computers, program memory was expensive and limited, and minimizing the size of a program in memory was important. Thus the code density -- the combined size of the instructions needed for a particular task -- was an important characteristic of an instruction set. Instruction sets with high code density employ powerful instructions that can implicity perform several functions at once. Typical complex instruction-set computers (CISC) have instructions that combine one or two basic operations (such as "add", "multiply", or "call subroutine") with implicit instructions for accessing memory, incrementing registers upon use, or dereferencing locations stored in memory or registers. Some software-implemented instruction sets have even more complex and powerful instructions. Reduced instruction-set computers (RISC), first widely implement during a period of rapidly-growing memory subsystems, traded off simpler and faster instruction-set implementations for lower code density (that is, more program memory space to implement a given task). RISC instructions typically implemented only a single implicit operation, such as an "add" of two registers or the "load" of a memory location into a register. Instruction sets may be categorized by the number of operands in their most complex instructions. (In the examples that follow, a, b, and c refer to memory addresses, and reg1 and so on refer to machine registers.) There has been research into executable compression as a mechanism for improving code density. The mathematics of Kolmogorov complexity describes the challenges and limits of this. List of ISAs This list is far from comprehensive as old architectures are abandoned and new ones invented on a continual basis. There are many commercially available microprocessors and microcontrollers implementing ISAs in all shapes and sizes. Customised ISAs are also quite common in some applications, e.g. ARC International, application-specific integrated circuit, FPGA, and reconfigurable computing. Also see history of computing hardware. ISAs commonly implemented in hardware ISAs commonly implemented in software with hardware incarnations ISAs never implemented in hardware Categories of ISA Examples of commercially available ISA Others | |||||||
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