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Pin spacing The most common DIPs have an inter-lead spacing (lead pitch) of 0.1" (2.54 mm) and a row spacing of either 0.3 in (7.62 mm) or 0.6 in (15.24 mm). Typical pin counts are 8 or any even number from 14 to 24 (less common 28) for 0.3 in packages, and 24, 28, 32 or 40 (less common 36, 48 or 52) for 0.6 in packages. Where there is a need to differentiate between the two widths for the same pin count the term "skinny dip" is used to refer to the 0.3 in version. JEDEC-standards also specify less common packages with a row spacing of 0.4 in (10.16 mm), or 0.9 in (22.86 mm) with a pin-count of up to 64. Other standardized variants include a lead pitch of 0.07 in (1.778 mm) at a row spacing of 0.3 in, 0.6 in or 0.75 in. In the former Soviet Union and Eastern bloc countries, similar packages were used with a metric inter-lead spacing of 2.5 mm, rather than 2.54 mm (or 0.1 in). Several DIP variants exist, mostly distinguished by packaging material: DIPs were the mainstream of the microelectronics industry in the 1970s and 80s. Their use has subsided in recent years due to the emerging new surface-mount technology (SMT) packages such as PLCC and SOIC. For programmable devices like EPROMs and GALs, DIPs remained popular for many years due to their easy handling with external programming circuitry. However, with In-System Programming (ISP) technology now state of the art, this advantage of DIPs is rapidly losing importance as well. Orientation and pin numbering DIPs have an orientation notch in one end. If the chip is held so that the long axis is horizontal and the notch is at the left end, pin See also | ||||||||||
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