yawiki.org entry for X86-64

	Navigation Home Recent Most Active Popular Blog Credits RSS
	Interaction Register Statistics
	Help Suggestions Contact Us How to Edit Help

x86-64 is a 64-bit microprocessor architecture and corresponding instruction set; it is a superset of the Intel x86 architecture, which it natively supports. It was designed by Advanced Micro Devices (AMD), who have since renamed it AMD64. This architecture has also been adopted by Intel under the names EM64T, IA-32e or Intel 64. The names x86-64 or x64 are sometimes used as vendor-neutral terms to collectively refer to the two nearly identical implementations.

    X86-64
        AMD64
            Architectural features
            Virtual address space details
            Operating modes
                Operating mode explanation
            AMD implementations
        EM64T
            History
            Summary from the Intel website
            Intel implementations
        Differences between AMD64 and EM64T
            Currently
            Previously
        Market analysis
        Operating system support
            DOS
            FreeBSD
            Linux
            Mac OS X
            MenuetOS
            NetBSD
            OpenBSD
            Solaris
            Windows
        Industry naming conventions
        See also

AMD64

The AMD64 instruction set is currently implemented in AMD's Athlon 64, Athlon 64 FX, Athlon 64 X2, Turion 64, Opteron and later Sempron processors.

Architectural features
AMD64 was created as an alternative to Intel and Hewlett Packard's radically different IA-64 architecture which has received a relatively cool market reception in many market sectors, and which was protected from cloning by a number of patents. The primary defining characteristic of AMD64 is its support for 64-bit general purpose registers, 64-bit integer arithmetic and logical operations, and 64-bit virtual addresses. The designers took the opportunity to make other improvements as well. The most significant changes include:

Full support for 64-bit integers: All general-purpose registers (GPRs) are expanded from 32 bits to 64 bits, and all arithmetic and logical operations, memory-to-register and register-to-memory operations, etc., are now directly supported for 64-bit integers. Pushes and pops on the stack are always in eight-byte strides, and pointers are eight bytes wide.

Additional registers: In addition to increasing the size of the general-purpose registers, their number is increased from eight (i.e. eax,ebx,ecx,edx,ebp,esp,esi,edi) in x86-32 to 16. It is therefore possible to keep more local variables in registers rather than on the stack and to let registers hold frequently accessed constants — this should be a significant area of speed improvement for software with computationally intensive deeply nested loops; arguments for small and fast subroutines may also be passed in registers to a greater extent. However, more registers also involves more saving and restoring of register contents, and AMD64 still has fewer registers than many common RISC processors (which typically have 31-64 registers) or VLIW-like machines such as the IA-64 (which has 128 registers).

Additional XMM registers: Similarly, the number of 128-bit XMM registers (used for Streaming SIMD instructions) is also increased from 8 to 16.

Larger virtual address space: Current processor models implementing the AMD64 architecture can address up to 256 tebibytes of virtual address space (2⁴⁸ bytes). This limit can be raised in future implementations to 16 exbibytes (2⁶⁴ bytes). This is compared to just 4 gibibytes for 32-bit x86. This means that very large files can be operated on by mapping the entire file into the process's address space (which is generally faster than working with file read/write calls), rather than having to map regions of the file into and out of the address space.

Larger physical address space: Current implementations of the AMD64 architecture can address up to 1 tebibyte of RAM (2⁴⁰ bytes); the architecture permits extending this to 4 pebibytes (2⁵² bytes) in the future (limited by the page table entry format). In legacy mode, Physical Address Extension (PAE) is supported, as it is on most current 32-bit x86 processors, allowing access to a maximum of 64 gibibytes.

Instruction pointer relative data access: Instructions can now reference data relative to the instruction pointer (RIP register). This makes position independent code, as is often used in shared libraries and code loaded at run time, more efficient.

SSE instructions: The original AMD64 architecture adopted Intel's SSE and SSE2 as core instructions. SSE3 instructions were added in April 2005. SSE2 replaces the x87 instruction set's IEEE 80-bit precision, with the choice of either IEEE 32-bit or 64-bit floating-point math. This provides floating-point operations compatible with many other modern CPUs. The SSE and SSE2 instructions have also been extended to support the eight new XMM registers. SSE and SSE2 are available in 32-bit mode in modern x86 processors; however, if they're used in 32-bit programs, those programs will only work on systems with processors that support them. This is not an issue in 64-bit programs, as all processors that support AMD64 support SSE and SSE2, so using SSE and SSE2 instructions instead of x87 instructions doesn't reduce the set of machines on which the programs will run. Since SSE and SSE2 are generally faster than, and duplicate most of the features of, the traditional x87 instructions, MMX, and 3DNow!, the latter are redundant under AMD64.

No-Execute bit: The “NX” bit (bit 63 of the page table entry) allows the operating system to specify which pages of virtual address space can contain executable code and which cannot. An attempt to execute code from a page tagged "no execute" will result in a memory access violation, similar to an attempt to write to a read-only page. This should make it more difficult for malicious code to take control of the system via "buffer overrun" or "unchecked buffer" attacks. A similar feature has been available on x86 processors since the 80286 as an attribute of segment descriptors; however, this works only on an entire segment at a time. Segmented addressing has long been considered an obsolete mode of operation, and all current PC operating systems in effect bypass it, setting all segments to a base address of 0 and a size of 4 GiB. AMD was the first x86-family vendor to support no-execute in linear addressing mode. The feature is also available in legacy mode on AMD64 processors, and recent Intel x86 processors, when PAE is used.

Removal of older features: A number of "system programming" features of the x86 architecture are not used in modern operating systems and are not available on AMD64 in long (64-bit and compatibility) mode. These include segmented addressing (although the FS and GS segments remain in vestigial form, for compatibility with Windows code), the task state switch mechanism, and Virtual-8086 mode. These features do of course remain fully implemented in "legacy mode," thus permitting these processors to run 32-bit and 16-bit operating systems without modification. If, at some point in the future, 32-bit and 16-bit code using those features is no longer used, support for them might be removed from hardware to streamline processor design and save manufacturing costs. These features could be emulated in the operating system to preserve legacy application compatibility, as with DOSBox and similar emulators.

Virtual address space details
Although virtual addresses are 64 bits wide in 64-bit mode, current implementations (and any chips known to be in the planning stages) do not allow the entire virtual address space of 2⁶⁴ bytes (16 exbibytes, or about 18×10¹⁸ bytes) to be used. Most operating systems and applications will not need such a large address space for the foreseeable future (for example, Windows implementations for AMD64 are only populating 16 tebibytes, or 44 bits' worth), so supporting such wide virtual addresses would simply increase the complexity and cost of address translation with no real benefit. AMD therefore decided that, in the first implementations of the architecture, only the least significant 48 bits of a virtual address would actually be used in address translation (page table lookup). However, bits 48 through 63 of any virtual address must be copies of bit 47 (in a manner akin to sign extension), or an exception will be raised. Addresses complying with this rule are referred to as "canonical form." Canonical form addresses run from 0 through 7FFF`FFFFFFFF, and from FFFF8000`00000000 through FFFFFFFF`FFFFFFFF, for a total of 2⁴⁸ bytes or 256 tebibytes of usable virtual address space.

This "quirk" allows an important feature for later scalability to true 64-bit addressing: traditionally, operating systems take one half of the address space for themselves (usually the higher half, named kernel space) and leave the other to applications (user space). The "canonical address" design ensures that every AMD64 compliant implementation has, in effect, two memory halves: the lower half starts at 00000000`00000000 and "grows upwards" as more virtual address bits become available, while the higher half is "docked" to the top of the address space and grows downwards.

The 64-bit addressing mode ("long mode") is a superset of Physical Address Extensions (PAE); because of this, page sizes may be either 4 KiB (2¹² bytes) or 2 MiB (2²¹ bytes). However, rather than the three-level page table system used by systems in PAE mode, systems running in long mode use four levels of page table: PAE's Page-Directory Pointer Table is extended from 4 entries to 512, and an additional Page-Map Level 4 Table is added, containing 512 entries in 48-bit implementations. In implementations supporting larger virtual addresses, this latter table would either grow to accommodate sufficient entries to describe the entire address range, up to a theoretical maximum of 33,554,432 entries for a 64-bit implementation, or be over ranked by a new mapping level, such as a PML5. Either way, a full mapping hierarchy of 4 KiB pages for the whole 48-bit space would take a bit more than 512 GiB of RAM (about 0.196% of the 256 TiB virtual space).

Operating modes

Operating mode explanation
There are two primary modes of operation for this architecture:

Long Mode: The intended primary mode of operation of the architecture; it is a combination of the processor's native 64-bit mode and a 32-bit/16-bit compatibility mode. It is used by 64-bit operating systems. Under a 64-bit operating system, 64-bit, 32-bit and 16-bit (or 80286) protected mode applications may be supported.

Since the basic instruction set is the same, there is no major performance penalty for executing x86 code. This is unlike Intel's IA-64, where differences in the underlying ISA means that running 32-bit code is like using an entirely different processor. However, on AMD64, 32 bit x86 applications may still benefit from a 64-bit recompile, due to the additional registers in 64-bit code, which a high-level compiler can use for optimization.

Legacy Mode: The mode used by 16-bit (protected mode or real mode) and 32-bit operating systems. In this mode, the processor acts just like an x86 processor, and only 16-bit or 32-bit code can be executed. 64-bit programs will not run.

AMD implementations

The following processors implement the x86-64 architecture:

AMD K8

AMD Athlon 64 X2

AMD Athlon 64 FX

AMD Sempron ("Palermo" E6 stepping and all "Manila" models)

Intel NetBurst (EM64T)

Intel Xeon (some models since "Nocona")

Intel Celeron D (some models since "Prescott")

Intel Pentium 4 (some models since "Prescott")

Intel Pentium D

Intel Pentium Extreme Edition

Intel Core microarchitecture (EM64T)

Intel Xeon ("Woodcrest")

EM64T
Extended Memory 64-bit Technology (EM64T) is Intel's implementation of AMD's AMD64.

During much of AMD's history, they have produced processors patterned after Intel's, but, in an ironic twist of computing history, AMD64 has been adopted (under the name EM64T or IA-32e) by Intel — the original creators of the x86 processor line—in newer versions of its Pentium 4, Pentium D, Pentium Extreme Edition, Celeron D, and Xeon processors, and in its Core 2 processors.

History
The EM64T project began with the codename Yamhill, named after the Yamhill River in Oregon's Willamette Valley. After several years of denying that this project existed, Intel eventually admitted it existed in early 2004, and gave it the codename CT (Clackamas Technology), also named after an Oregon river, the Clackamas. Then within the space of weeks of the CT announcement, Intel gave it several new names. After the spring 2004 IDF, Intel named it IA-32E (IA-32 Extensions) and a few weeks later devised the name EM64T. Intel's chairman at the time, Craig Barrett, admitted that this was one of their worst kept secrets. refers to the instruction set as "Intel64".

Summary from the Intel website
Intel EM64T improves performance by allowing the system to address more than 4 GiB of both virtual and physical memory. Intel EM64T provides support for:

64-bit flat virtual address space

64-bit pointers

64-bit wide general purpose registers

64-bit integer support

Up to 1 tebibyte (TiB) of platform address space

Intel implementations
EM64T was originally implemented on the E revision (Prescott) of Pentium 4 line of microprocessors, which were supported by i915P (Grantsdale) and i925X (Alderwood) chipsets in June 2004. EM64T's implementation was largely due to the competitive pressure of AMD's AMD64 technology implemented on Opteron and Athlon64 lines of microprocessing units, otherwise known as the K8 core, one year earlier in 2003; and the technology was largely built compatible to AMD64, and the then announced Windows XP Professional x64 Edition supporting AMD64 technology. Intel's first processor to activate the EM64T technology was the multi-socket processor Xeon codenamed Nocona. Since the Nocona Xeon itself is directly based on Intel's desktop processor, the Pentium 4, the Pentium 4 also has EM64T technology built in, although as with Hyper-Threading, this feature was not initially enabled on the then-new Prescott design, likely because enabling EM64T did not coincide with Intel's stance on x86-64 extensions at that particular time. Intel has since begun selling EM64T enabled Pentium 4s using the E0 revision of the Prescott core, being sold on the market as the Pentium 4, model F. However, the revision F core was targeted at workstations. Intel's official launch of EM64T to desktop was the N0 Stepping Prescott-2M. The E0 revision also adds eXecute Disable(XD) support to EM64T, Intel's name for the NX bit, and has been included in the current Xeon codenamed Irwindale. All 9xx/8xx/6xx/5x6/5x1/3x6/3x1 series CPUs have EM64T enabled, as do the Core 2 CPUs, and as will all future Intel CPUs. EM64T is also present in the last members of the Celeron D line.

The first Intel mobile processor supporting EM64T is the Merom version of the Core 2 processor, which was released on 27 July 2006. None of Intel's earlier notebook CPUs (Core Duo, Pentium M, Celeron M, Mobile Pentium 4) support EM64T.

Differences between AMD64 and EM64T
There are a small number of differences between each instruction set. Compilers generally produce binaries that target both AMD64 and EM64T, making the differences mainly of interest to compiler developers and operating system developers.

Currently

EM64T's BSF and BSR instructions act differently when the source is 0 and the operand size is 32 bits. The processor sets the zero flag and leaves the upper 32 bits of the destination undefined.

AMD64 supports 3DNow! instructions. This includes prefetch with the opcode 0x0F 0x0D and PREFETCHW, which are useful for hiding memory latency.

EM64T lacks the ability to save and restore a reduced (and thus faster) version of the floating-point state (involving the FXSAVE and FXRSTOR instructions).

EM64T lacks some model-specific registers that are considered architectural to AMD64. These include SYSCFG, TOP_MEM, and TOP_MEM2.

EM64T supports microcode update as in 32-bit mode, although it has been rumored that AMD processors have supported programmable microcode as an undocumented feature for years.

EM64T's CPUID instruction is very vendor-specific, as is normal for x86-style processors.

EM64T supports the MONITOR and MWAIT instructions, used by operating systems to better deal with Hyper-threading.

AMD64 systems allow the use of the AGP aperture as an IO-MMU. Operating systems can take advantage of this to let normal PCI devices DMA to memory above 4 GiB. EM64T systems require the use of bounce buffers, which are slower.

SYSCALL and SYSRET are also only supported in IA-32e mode (not in compatibility mode) on EM64T. SYSENTER and SYSEXIT are supported in both modes.

Near branches with the 0x66 (operand size) prefix behave differently. One type of CPU clears only the top 32 bits, while the other type clears the top 48 bits.

Previously

Early AMD64 processors lacked the CMPXCHG16B instruction, which is an extension of the CMPXCHG8B instruction present on most post-486 processors. Similar to CMPXCHG8B, CMPXCHG16B allows for atomic operations on 128-bit double quadword (or oword) data types. This is useful for high resolution counters that could be updated by multiple processors (or cores). Without CMPXCHG16B the only way to perform such an operation is by using a critical section.

Early Intel CPUs with EM64T lacked LAHF and SAHF instructions supported by AMD64 until introduction of Pentium 4 G1 step in December 2005. LAHF and SAHF are load and store instructions, respectively, for certain status flags. These instructions are used for virtualization and floating-point condition handling.

Early Intel CPUs with EM64T also lack the NX bit (No Execute bit) of the AMD64 architecture. The NX bit marks memory pages as non-executable, allowing protection against many types of malicious code.

Originally EM64T hardware allowed access only to 2³⁶ bytes of memory, while AMD64 systems can handle up to 2⁴⁰ bytes (with planned expansion to 2⁵⁶ bytes). However, as of recent publications, EM64T now provides 2⁴⁰ bytes of memory access.

Market analysis
AMD's AMD64 design represents a break with the company's past behavior of following Intel's standards, but emulates Intel's earlier behavior of extending the x86 architecture, from the 16-bit 8086 to the 32-bit 80386 and beyond, without ever removing backward compatibility.

It was believed at one point that 64-bit RISC chips such as the DEC Alpha would eventually replace the outdated and quirky x86 architecture. Part of the reason this did not happen was the vast investment in application software for x86-based systems. The x86-64 architecture effectively migrates the x86 architecture into a fully 64-bit environment, while maintaining legacy compatibility with x86 applications.

As of 2006, most consumer and business applications have not evolved into 64-bit aware software. Most current software applications do not need to address more than 2 GiB of memory. Nevertheless, the chips' cost-effectiveness has allowed AMD to capture a larger share of the personal computer market, at Intel's expense, simply because of the performance to cost ratio and the expected growth capability should 64-bit applications become common. Intel in the summer of 2006 had announced a substantial reduction in net revenue and major restructuring.

Operating system support
The following operating systems and releases support the x86-64 architecture in long mode.

DOS
It is possible to enter long mode under DOS with a DOS extender similar to DOS4GW. DOS itself is not aware of that and no benefits should be expected unless running DOS in an emulation with an adequate virtualization driver backend, for example: the mass storage interface.

FreeBSD
FreeBSD first added x86-64 support as an experimental architecture in 5.1-RELEASE. Since then, FreeBSD has designated the x86-64 architecture as a Tier 1 platform. The 6.0-RELEASE version cleaned up some quirks with running 32-bit executables under AMD64, and most drivers work just as they do on 32-bit x86 architectures. Work is currently being done to fully integrate the 32-bit x86 application binary interface (ABI), in the same manner as the Linux's 32-bit ABI compatibility currently works. Within the FreeBSD environment and developer code base, the x86-64 architecture is usually referred to as "amd64".

Linux
Linux was the first operating system kernel to run the x86-64 architecture in long mode, starting with the 2.4 version prior to the physical hardware's availability. Linux also provides backward compatibility for running 32-bit executables. This permits programs to be recompiled into long mode while retaining the use of 32-bit programs. CentOS, Debian, Fedora, Frugalware, Gentoo, Kanotix, Mandriva, Novell, PLD, Red Hat, Source Mage, SUSE and Ubuntu Linux distributions currently ship with x86-64-native kernels and userlands. Some, such as SUSE, package both 32-bit and 64-bit systems on a single DVD-ROM image to allow automatic selection of the best software during installation. The Debian team has announced that their next release (Debian GNU/Linux 4.0 alias etch) will officially support the x86-64 architecture.

Mac OS X
Apple Computer has indicated that Mac OS X 10.5 will support 64-bit applications on its 64-bit x86-based machines as well as on 64-bit PowerPC machines. Mac OS X 10.4.7 and higher support 64-bit command-line tools when run on 64-bit x86-based machines, just as version 10.4 and higher support them on 64-bit PowerPC machines.

MenuetOS
The AMD64 version of MenuetOS was released in June 2005. Although MenuetOS was originally written for 32-bit x86 architectures and released under the GPL, the AMD64 version is proprietary. It is distributed as freeware with the source code for some components.

NetBSD
Support for the x86-64 architecture was first committed to the NetBSD source tree on 19 June 2001. As of NetBSD 2.0, released on 9 December 2004, NetBSD/amd64 is a fully integrated and supported port.

OpenBSD
OpenBSD has supported AMD64 since OpenBSD 3.5, released on 1 May 2004. Complete in-tree support for the platform was achieved prior to the hardware's initial release due to AMD's loaning of several machines for the project's hackathon that year. OpenBSD developers have taken to the platform because of its use of the NX bit, which allowed for an easy implementation of the W^X feature.

The code for the AMD64 port of OpenBSD also runs on the Intel processors with EM64T support which contain cloned support for the AMD64 extensions, but since Intel left out support for the page table NX bit in early EM64T processors, there is no W^X support on those Intel CPUs; later Intel EM64T processors added support for the NX bit under the name "XD bit". Symmetric multiprocessing (SMP) is supported on OpenBSD's AMD64 port, starting with release 3.6 on 1 November 2004.

Solaris
Solaris 10 and later releases support the x86-64 architecture. Just as with the SPARC architecture, there is only one operating system image for all 32-bit and 64-bit x86 systems; this is labeled as the "x86/x64" DVD-ROM image.

Default behavior is to boot a 64-bit kernel, allowing both 64-bit and existing or new 32-bit executables to be run. A 32-bit kernel can also be manually selected, in which case only 32-bit executables are supported. The isalist command can be used to determine if a system is running a 64-bit kernel.

Windows
x64 editions of Microsoft Windows client and server, Windows XP Professional x64 Edition and Windows Server 2003 SP1 x64 Edition, were released in March 2005. Internally they are actually the same build (5.2.3790.1830 SP1), as they share the same source base and operating system binaries, so even system updates are released in unified packages, much in the manner as Windows 2000 Professional and Server editions for x86. Windows for x64 has the following characteristics:

8 tebibytes (2⁴³ bytes) of user mode virtual address space per process. A 64-bit program can use all of this, subject of course to backing store limits on the system. This is a 4096-fold increase over the default 2 gibibyte user-mode virtual address space offered by 32-bit Windows.

8 tebibytes (2⁴³ bytes) of kernel mode virtual address space for the operating system. Again, this is a 4096-fold increase over 32-bit Windows versions. The increased space is primarily of benefit to the file system cache and kernel mode "heaps" (non-paged pool and paged pool).

Support for up to 128 GiB (Windows XP) or 1 TiB (Windows Server 2003) of RAM.

LLP64 data model: "int" and "long" types are still 32 bits wide, while pointers and types derived from pointers are 64 bits wide.

Device drivers must be 64-bit versions; there is no support for running 32-bit kernel-mode executables within the 64-bit OS.

Support for running existing 32-bit applications (.exe's) and dynamic link libraries (.dll's). A 32-bit program, if linked with the "large address aware" option, can use up to 4 gibibytes of virtual address space, as compared to the default 2 gibibytes (optional 3 gibibytes with /3GB boot.ini option and "large address aware" link option) offered by 32-bit Windows.

16-bit DOS and Windows (Win16) applications will not run on x64 versions of Windows due to removal of NTVDM.

Full implementation of the NX (No Execute) page protection feature. This is also implemented on recent 32-bit versions of Windows when they are started in PAE mode.

As in x86 versions of the Windows NT family, the FS and GS segment descriptors are used to point to two operating-system defined structures: the Thread Information Block and Processor Control Region, respectively. Thus, for example, FS:0 is the address of the first member of the Thread Information Block. Maintaining this convention made the x64 port easier, but required AMD to retain the function of the FS and GS segments in long mode — even though segmented addressing per se is not really used by any modern operating system.

Early reports claimed that the operating system scheduler would not save and restore the x87 FPU machine state across thread context switches. Observed behavior shows that this is not the case: the x87 state is saved and restored, except for kernel-mode-only threads. Nevertheless, the most recent documentation available from Microsoft states that the x87/MMX/3DNow! instructions may not be used in long mode.

Some components like Microsoft Jet Database Engine and Data Access Objects will not be ported to the x86-64 architecture.

Industry naming conventions
Since AMD64 and EM64T are substantially similar, it is convenient to have a vendor-neutral way to designate products that support both implementations. AMD's original designation for this processor architecture, "x86-64", is still sometimes used for this purpose. The Linux kernel and Apple's Mac OS X• uses the variant "x86_64".

Similarly, Microsoft began using "x64" as a vendor-neutral way to refer to products that support both AMD64 and EM64T. Other companies, such as Sun Microsystems, have also adopted this convention.

Internally, x64 versions of Windows use the AMD64 moniker to designate various components which use 64-bit technology for IA-32 processors (for example, the system folder on a Windows x64 Edition installation CD-ROM is named "AMD64" instead of "i386" in 32-bit versions). Similarly, the isalist command in Sun's Solaris operating system identifies both AMD64- and EM64T-based systems as "amd64"; largely due to the fact that Solaris support for this processor architecture predated the existence of Intel's EM64T extensions and the x64 term. Likewise, other operating system, such as Gentoo Linux, FreeBSD and NetBSD support both AMD64 and EM64T under the architecture name "amd64".

See also

	Source Privacy License Download Contact Us Atlas Scientus.org Dictionary (Yet Another Wiki) RC : 1.39 This article is licensed under the GNU Free Documentation License [copyleft]. It uses material from the Wikipedia article "X86-64". link